Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 39th annual Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Proceedings of the 2002 international symposium on Low power electronics and design
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
FLUTE: fast lookup table based wirelength estimation technique
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient algorithms for buffer insertion in general circuits based on network flow
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
Power optimization in a repeater-inserted interconnect via geometric programming
Proceedings of the 2006 international symposium on Low power electronics and design
A Low-Power Multi-Pin Maze Routing Methodology
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
FastRoute 2.0: A High-quality and Efficient Global Router
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Maze routing with buffer insertion and wiresizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MARS-a multilevel full-chip gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Practical repeater insertion for low power: what repeater library do we need?
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate estimation of global buffer delay within a floorplan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the ever increasing die sizes and the accompanied increase in the average global interconnect length, delay-optimal-routing and buffer-insertion techniques are significantly straining the power budget of modern ICs. To mitigate the impact of the power consumed by the interconnects and buffers, a power-efficient multipin routing technique is proposed in this paper. The problem is based on a graph representation of the routing possibilities, with the objective of identifying the minimum power path between the interconnect source and set of sinks. The technique is tested by applying it to the International Symposium on Physical Design and IBM benchmarks to verify the accuracy, complexity, and solution quality. Results obtained indicate that an average power saving as high as 32% for the 130-nm technology is achieved with no impact on the maximum chip frequency.