Optimization of inductor circuits via geometric programming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low Power Digital CMOS Design
Optimizing dominant time constant in RC circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Supply and power optimization in leakage-dominant technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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We present an innovative geometric programming (GP) approach for minimizing the power dissipation of an interconnect with repeater insertion, subject to delay, bandwidth and area constraints. Repeater sizes and segment lengths are globally optimized in various technology nodes with respect to International Technology Roadmap for Semiconductors (ITRS). Relative power dissipation due to different power components is analyzed. We show that, on average, the power dissipation per unit length can be reduced by over 30% when the timing constraint is relaxed by 5%. The optimum number of repeaters is always given as an integer in our design flow. The relationships between power dissipation and respective design constraints are easily visualized in tradeoff curves. Additional design criteria, such as reliability of the interconnect delay against process variations, are easily incorporated into the optimization.