Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology

Authors:
Koichi Nose;Takayasu Sakurai
Affiliations:
Institute of Industrial Science, University of Tokyo, Tokyo, Japan;Institute of Industrial Science, University of Tokyo, Tokyo, Japan
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

Citing 2
Cited 1

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects

Proceedings of the 38th annual Design Automation Conference

A power-efficient multipin ILP-based routing technique

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Closed-form formulas for optimum buffer insertion where the junction capacitance is taken into account are proposed. In order to use the derived formulas, an appropriate choice of the effective linear resistance of the driving transistor is also clarified.Using the proposed formulas, the optimum interconnect delay and power comparison between bulk and SOI CMOS technology are discussed.The calculation results show that both the optimum delay and power with SOI can be reduced by 15% compared with the bulk MOSFET whose junction capacitance is assumed to be equal to the gate capacitance.