A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
Microelectronics Journal
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This paper investigates the problem of repeater insertion for low power under a given timing budget. A novel repeater insertion algorithm is proposed to compute the optimal repeater number and width in the discrete solution space, as defined by a given repeater library. Using the proposed algorithm, two practical and highly important questions are addressed. Given a certain tolerance to the degradation of repeater power dissipation: 1) how coarse could the repeater size granularity be? 2) What range should repeater widths be in? The experimental results provide valuable insights into repeater library design. Specifically, the investigation reveals that coarse repeater size granularities can be used to reduce the library size by more than 87% with merely a 4% power degradation. Moreover, for two-pin interconnects with various wire lengths and timing targets, the range of optimal repeater sizes for low power is limited, indicating that a low-cost small-size repeater library, if well designed, is adequate to provide high-quality repeater insertion solutions. The proposed scheme can be used in early design stages to generate a compact repeater library that is passed on to other repeater insertion algorithms.