A yield-driven gridless router
Journal of Computer Science and Technology
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
Embedding repeaters in silicon IPs for cross-IP interconnections
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing problem as a graph-theoretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamic programming based techniques. Routing constraints such as wiring obstacles and restrictions on buffer locations and types are easily incorporated in the formulation. They construct a buffer planning (BP)-graph such that the length of every path in this graph is equal to the Elmore delay. Therefore, finding the minimum Elmore delay path becomes a finite shortest path problem. The buffer choices and insertion locations are represented as the vertices in the BP-graph. The interconnect wires are sized by constructing a look-up table for buffer-to-buffer wiresizing solutions. The authors also provide a technique that is able to tremendously improve the runtime. Experiments show improvements over previously proposed methods.