What is the design challenge for on-chip speed-of-light communication?

  • Authors:
  • C. K. Cheng;James Buckwalter

  • Affiliations:
  • Univ. of California at San Diego;Univ. of California at San Diego

  • Venue:
  • ACM SIGDA Newsletter
  • Year:
  • 2008

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Abstract

As technology scales, on-chip interconnects become one of the most critical factors in determining the system performance and power consumption [1-3]. Since the wire resistance per unit length is inversely proportional to its cross section, the wire incurs high-signal attenuation as its cross section shrinks. Current practice views the wires as RC segments. Buffers are inserted between RC segments to boost a faster full voltage swing [4,5]. The inserted buffers regenerate the voltage level from buffer inputs instead of relaying the signals as waves. The full swing of RC segments requires high latency and consumes power.