Digital systems engineering
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
On-Chip Interconnect Inductance - Friend or Foe (Invited)
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Evaluation of on-chip transmission line interconnect using wire length distribution
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low power passive equalizer optimization using tritonic step response
Proceedings of the 45th annual Design Automation Conference
High performance on-chip differential signaling using passive compensation for global communication
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A 9-Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
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We describe an interconnect scheme based on lossy transmission lines, compare this scheme with traditional bus based links, and present performance data. Unlike some other schemes there is no requirement for up-conversion, equalization, or special metal processing. In preliminary work, we have measured data rates of 14 Gbps (limited by test equipment) over a 7.2 mm interconnection, implemented in 0.18 /spl mu/m CMOS. For active links signaling over a single serial link, is more power efficient than over traditional parallel buses, does not require repeaters and is less affected by noise and coupling.