Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Global signaling over lossy transmission lines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Equalized interconnects for on-chip networks: modeling and optimization framework
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Low power passive equalizer optimization using tritonic step response
Proceedings of the 45th annual Design Automation Conference
High-speed signal propagation: advanced black magic
High-speed signal propagation: advanced black magic
Low Power Passive Equalizer Design for Computer Memory Links
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Prediction of high-performance on-chip global interconnection
Proceedings of the 11th international workshop on System level interconnect prediction
Placement and beyond in honor of Ernest S. Kuh
Proceedings of the 2011 international symposium on Physical design
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To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is proposed and optimized. We propose a signaling structure to compensate the distortion and attenuation of on-chip transmission lines, which uses passive compensation and inserts repeated transceivers composing sense amplifiers and inverter chains. An optimization flow for designing this scheme based on eye-diagram prediction and sequential quadratic programming (SQP) is devised. This flow is used to study the latency, power dissipation and throughput performance of the new global wiring scheme as the technology scales from 90 nm to 22 nm. Comparing to repeated RC wire, experimental results demonstrate that at 22 nm technology node, the new scheme can reduce the normalized delay by 80%-95%, the normalized energy consumption by 50%-94%. The normalized latency is 10 ps/mm, the energy per bit is 20 pJ/m, and the throughput is 15 Gbps/μm. All performance metrics are scalable with technology, which makes this approach a potential candidate to break the "interconnect wall" of digital system performance.