Proceedings of the 2008 Asia and South Pacific Design Automation Conference
High performance on-chip differential signaling using passive compensation for global communication
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Prediction of high-performance on-chip global interconnection
Proceedings of the 11th international workshop on System level interconnect prediction
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
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As semiconductor process technologies scale down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization and delay2-power minimization. We show how various design criteria influence interconnect performance: (1) the optimal inverter to wire capacitance ratio depends only on the technology and design goal, not on wire pitch, (2) at min-pitch, the width pitch ratios of wire for different objective functions are different: the ratio is 0.52 for minimizing delay, 0.31 for minimizing delay2- power product and 0.21 for minimizing delay-power product, (3) the quantitative delay-energy trade-offs for the three objective functions are: the delay-power product reduces power by 67% with a cost of 40% larger delay, while the delay2-power product reduces power by 50% with a cost of 10% larger delay, which implies that delay2-power product results a decent power saving with little cost on speed and (4) the quantitative results of the impact of wire pitch on wire performance are derived. Particularly at 70nm technology node, for bandwidth, the optimal pitch is at min-pitch, while for power, the optimal pitch is 2.35x the min-pitch, and for bandwidth over power, the optimal pitch is 1.76x min-pitch.