Performance prediction of throughput-centric pipelined global interconnects with voltage scaling

Authors:
Yulei Zhang;James F. Buckwalter;Chung-Kuan Cheng
Affiliations:
University of California, San Diego, La Jolla, USA;University of California, San Diego, La Jolla, USA;University of California, San Diego, La Jolla, USA
Venue:
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Year:
2010

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Abstract

Due to the ever increasing demand for computing capacity, throughput-centric design for on-chip global interconnects has played an important role in the emerging parallel computing architectures. In this paper, we explore the performance of flip-flop-based pipelined global interconnects with more design freedoms under the voltage and technology scaling for different applications. Based on the derived accurate voltage-scaled models of pipelined interconnects, we propose a general evaluation flow using numerical experiments to study the impact of pipelining depth, voltage scaling, and different processes on the performance of pipelined interconnects under four different design objectives. Our experimental results show that, with the dedicated throughput-centric optimization, at 45 nm node, up to 25x overall throughput-per-energy-area (TPEA) improvement can be obtained with only 4x increase on the interconnect latency compared with the conventional minimum-latency design, making this new design methodology more promising in the future nodes.