Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Equalized interconnects for on-chip networks: modeling and optimization framework
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient and accurate eye diagram prediction for high speed signaling
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
High performance on-chip differential signaling using passive compensation for global communication
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Scalable high-radix router microarchitecture using a network switch organization
ACM Transactions on Architecture and Code Optimization (TACO)
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Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of current on-chip global interconnection structures and provide a simple model to analyze their architecture-level performance metrics. For a new category of global interconnections using on-chip transmission-line (T-line), a general framework is proposed to design and optimize such schemes. A group of experiments is performed to study and compare five different global interconnection structures in terms of latency, energy dissipation, throughput, and signal integrity across multiple technology nodes. The results show that, the T-line structures have the potential to outperform repeated RC wires at future nodes to achieve high-performance, low-power and more reliable global interconnection. Meanwhile, equalization could be helpful to improve the throughput, signal integrity, and power efficiency further.