Performance-driven system partitioning on multi-chip modules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Quadratic Boolean programming for performance-driven system partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Floorplan sizing by linear programming approximation
Proceedings of the 37th Annual Design Automation Conference
The Chebyshev expansion based passive model for distributed interconnect networks
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
I/O Pad Assignment Based on the Circuit Structure
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An MCM/IC Timing-Driven Placement Algorithm Featuring Explicit Design Space Exploration
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Fast heuristic techniques for placing and wiring printed circuit boards
Fast heuristic techniques for placing and wiring printed circuit boards
SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits
EURO-DAC '91 Proceedings of the conference on European design automation
APlace: a general analytic placement framework
Proceedings of the 2005 international symposium on Physical design
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An unconditional stable general operator splitting method for transistor level transient analysis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient transient simulation for transistor-level analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low power passive equalizer optimization using tritonic step response
Proceedings of the 45th annual Design Automation Conference
Low Power Passive Equalizer Design for Computer Memory Links
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Efficient and accurate eye diagram prediction for high speed signaling
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
High performance on-chip differential signaling using passive compensation for global communication
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Two-Stage Newton–Raphson Method for Transistor-Level Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Professor Kuh is a pioneer and giant in physical layout. In this talk, we will describe his influence in placement. His pioneering work from interval graph for one dimensional gate assignment, BBL (Building-Block Layout System for Custom Chip IC Design) [2, 3, 6, 8], BEAR [7] layout system, BAGEL (Gate Array Layout) [17], RAMP (Resistive Analog Module Placement) [5], PROUD (Sea of Gates Placement) [28] to congestion, timing, and low power driven placement, Prof. Kuh always starts with innovative theoretical construction, software system building, and applications with impact on productivity. Physical layout is an indispensable software system for VLSI Design with millions of modules. Placement is the key component of about 500 million dollars market for physical synthesis. In the layout design flow, the placement is the core of the system integrating with other synthesis and analysis tools. For building block layout, Kuh's group tackled the nonslicing architecture. They devised the tile plane to represent the topology of the floorplan and the bottleneck of the routing. A routing order is derived to guarantee 100 percent routing completion [12]. The methodology and algorithms of building block placement [2] were adopted by companies such as Digital Equipment Corporation and ECAD, which was later renamed as Cadence. For standard cell placement, RAMP placement is devised using the analogy of a resistive network [12]. The minimization of the circuit power corresponds to the quadratic wire length reduction. The approach provides a convergent solution in the era of interconnect dominance. As the technology scales, interconnect becomes dominating the system performance in terms on delay and power consumption. Performance driven logic synthesis, signal interconnect with repeater insertion, power ground and clock distribution strongly rely on the physical layout information. On the other hand the placement requires the synthesis result to perform the task. This mutual dependence has caused serious design convergence issues in the 1990s.