EXPLORER: an interactive floorplanner for design space exploration
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A New Timing-Driven Multilayer MCM/IC Routing Algorithm
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Placement and beyond in honor of Ernest S. Kuh
Proceedings of the 2011 international symposium on Physical design
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A genetic algorithm for building-block placement of MCMs and ICs is presented which simultaneously minimizes layout area and an Elmore-based estimate of the maximum path delay while trying to meet a target aspect ratio. Explicit design space exploration is performed by using a vector-valued, 3-dimensional cost function and searching for a set of distinct solutions representing the best tradeoffs of the cost dimensions. Designers can then choose from the output set of feasible solutions. In contrast to existing approaches such as simulated annealing, neither weights nor bounds are needed, thereby eliminating the inherent practical problems of specifying these quantities. Promising results are obtained for various placement problems, including a real-world MCM design.