Branch-and-bound placement for building block layout

  • Authors:
  • Hidetoshi Onodera;Yo Taniguchi;Keikichi Tamaru

  • Affiliations:
  • Department of Electrical Engineering and Computer Siences, University of California, Berkeley, CA and Department of Electronics, Kyoto University, Sakyo-ku, Kyoto 606 Japan;Department of Electronics, Kyoto University, Sakyo-ku, Kyoto 606 Japan;Department of Electronics, Kyoto University, Sakyo-ku, Kyoto 606 Japan

  • Venue:
  • DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
  • Year:
  • 1991

Quantified Score

Hi-index 0.00

Visualization

Abstract