A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Integrated placement for mixed macro cell and standard cell designs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
MHERTZ: a new optimization algorithm for floorplanning and global routing
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Transistor level placement for full custom datapath cell design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
System-level routing of mixed-signal ASICs in WREN
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Analytical approach to custom datapath design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Macro Block Based FPGA Floorplanning
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A new clustering approach and its application to BBL placement
EURO-DAC '90 Proceedings of the conference on European design automation
Mickey: a macro cell global router
EURO-DAC '91 Proceedings of the conference on European design automation
Concurrent Placement and Routing in the Design of Integrated Circuits
Automation and Remote Control
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Algorithms and theory of computation handbook
Composite stock cutting through simulated annealing
Mathematical and Computer Modelling: An International Journal
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The algorithms and the implementation of a new macro/custom cell chip-planning, placement, and global routing package are presented. The simulated-annealing-based placement algorithm proceeds in two stages. In the first stage, the interconnect area around the individual cells is determined using a new dynamic interconnect area estimator. The second stage consists of: (1) a channel definition step, using a new channel definition algorithm, (2) a global routing step, using a new global router algorithm, and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interconnect length savings of 8 to 49 percent were achieved in experiments on 9 industrial circuits. Furthermore, circuit-area reductions ranged from 4 to 56 percent versus a variety of other placement methods.