Concurrent Placement and Routing in the Design of Integrated Circuits

Authors:
A. I. Erzin;J. D. Cho
Affiliations:
Sobolev Institute of Mathematics, Siberian Branch, Russian Academy of Sciences, Novosibirsk, Russia;Sungkyunkwan University, Suwon, South Korea
Venue:
Automation and Remote Control
Year:
2003

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Abstract

For the problem arising in the design of integrated chips, an efficient heuristic approach was proposed. It unites the stages of placing the logical elements (devices) on the chip and performing their detailed routing. At that, it minimizes both the critical (maximum) delay and the chip area required for routing.