An integrated algorithm for combined placement and libraryless technology mapping

Authors:
Yanbin Jiang;Sachin S. Sapatnekar
Affiliations:
Cadence Design Systems, Inc., San Jose, CA;Department of ECE, University of Minnesota, Minneapolis, MN
Venue:
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Year:
1999

Citing 11
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Abstract

This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless mapping and a state space search mechanism that is used to find the best solution. Several heuristics are presented for speeding up the search. Comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable CPU times, on benchmark circuits.