Library-less synthesis for static CMOS combinational logic circuits

Authors:
S. Gavrilov;A. Glebov;S. Pullela;S. C. Moore;A. Dharchoudhury;R. Panda;G. Vijayan;D. T. Blaauw
Affiliations:
Research Institute for VLSI CAD Systems, Russian Academy of Sciences, Moscow Russia;Research Institute for VLSI CAD Systems, Russian Academy of Sciences, Moscow Russia;Unified Design Systems Laboratory, Motorola, Austin;Unified Design Systems Laboratory, Motorola, Austin;Unified Design Systems Laboratory, Motorola, Austin;Unified Design Systems Laboratory, Motorola, Austin;Unified Design Systems Laboratory, Motorola, Austin;Unified Design Systems Laboratory, Motorola, Austin
Venue:
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Year:
1997

Citing 11
Cited 13

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation

DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993

Surveys in combinatorics, 1993
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A survey of optimization techniques targeting low power VLSI circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic extraction and factorization for low power

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transistor reordering for low power CMOS gates using an SP-BDD representation

ISLPED '95 Proceedings of the 1995 international symposium on Low power design
CELLERITY: a fully automatic layout synthesis system for standard cell libraries

DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast power loss calculation for digital static CMOS circuits

EDTC '97 Proceedings of the 1997 European conference on Design and Test
Delay optimization of digital CMOS VLSI circuits by transistor reordering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

An integrated algorithm for combined placement and libraryless technology mapping

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
CMOS combinational circuit sizing by stage-wise tapering

Proceedings of the conference on Design, automation and test in Europe
Technology mapping for high-performance static CMOS and pass transistor logic designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimized power-delay curve generation for standard cell ICs

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Exact lower bound for the number of switches in series to implement a combinational logic cell

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Fast disjoint transistor networks from BDDs

SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Modeling and estimating leakage current in series-parallel CMOS networks

Proceedings of the 17th ACM Great Lakes symposium on VLSI
DAG based library-free technology mapping

Proceedings of the 17th ACM Great Lakes symposium on VLSI
A comparative study of CMOS gates with minimum transistor stacks

Proceedings of the 20th annual conference on Integrated circuits and systems design
A methodology for transistor-efficient supergate design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Contributions to the evaluation of ensembles of combinational logic gates

Microelectronics Journal
Power reduction via separate synthesis and physical libraries

Proceedings of the 48th Design Automation Conference
Subthreshold leakage modeling and estimation of general CMOS complex gates

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. The authors present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. The technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of the resynthesized circuits.