Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A semi-custom design flow in high-performance microprocessor design
Proceedings of the 38th annual Design Automation Conference
Optimized power-delay curve generation for standard cell ICs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We introduce the concept of utilizing two cell libraries, one for synthesis and another for physical design. The physical library consists of only 9 functions, each with several drive and beta ratio options, for a total cell count of 186. We show that synthesis performs better with the inclusion of more complex cells (but only if they are power efficient), we augment the synthesis library to include numerous combinations of the basic 9 functions. The resulting synthesis library consists of a total of 865 cells. Note that these compound cells require only characterization (for a set of drive strengths, but only one beta ratio) and no layout. After design synthesis the compound cells are decomposed back to the basic (9) cells in the physical library. Then cell-size optimization is performed. The entire flow is efficient, with an ability to handle multi-million-gate commercial designs. Applied after state-of-the-art commercial synthesis, the application of a discrete cell-size selection tool, combined with the new dual library approach, results in a typical active area reduction of 40% for large current industrial designs, for the same delay.