What is the state of the art in commercial EDA tools for low power?
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Cell libraries—build vs. buy; static vs. dynamic (panel)
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A semi-custom design flow in high-performance microprocessor design
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Efficient timing closure without timing driven placement and routing
Proceedings of the 41st annual Design Automation Conference
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automated Design Space Exploration for DSP Applications
Journal of Signal Processing Systems
Power reduction via separate synthesis and physical libraries
Proceedings of the 48th Design Automation Conference
Efficient post-layout power-delay curve generation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An effective way to compare logic techniques, logic families, or cell libraries is by means of power (or area) versus delay plots, since the efficiency of achieving a particular delay is of crucial significance. In this paper we describe a method of producing an optimized power versus delay curve for a combinational circuit. We then describe a method for comparing the relative merits of a set of power versus delay curves for a circuit, each generated with a different cell library. Our results indicate that very few combinational functions need to be in a cell library, at most 11. The power-delay points achieved by Design Compiler from Synopsys using the state-of-the-art Artisan Sage-X library compare unfavorably to our approach. In terms of minimum energy-delay product, our approach is superior by 79% on average. Our approach yields the same delay points with a 107% savings in power consumption, on average. We also show that the specified VDD for a process technology should only be used for the absolute fastest implementations of a circuit.