Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An Adaptive Nonlinear Least-Squares Algorithm
ACM Transactions on Mathematical Software (TOMS)
On the signal bounding problem in timing analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimized power-delay curve generation for standard cell ICs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient timing closure without timing driven placement and routing
Proceedings of the 41st annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JiffyTune: circuit optimization using time-domain sensitivities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact transistor sizing based on iterative relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaRS: parallel and near-optimal grid-based cell sizing for library-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Fast and efficient lagrangian relaxation-based discrete gate sizing
Proceedings of the Conference on Design, Automation and Test in Europe
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model is used in a new version of a gate-sizing tool called Forge, which not only exhibits optimality, but also efficiently produces the area versus delay trade-off curve for a block in one step. Forge includes a realistic delay propagation scheme that combines arrival times and slew-rates. Forge is 6.4X faster than a commercial transistor sizing tool, while achieving better delay targets and uses 28% less transistor area for specific delay targets, on average.