Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lagrangian relaxation for gate implementation selection
Proceedings of the 2011 international symposium on Physical design
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
The ISPD-2012 discrete cell sizing contest and benchmark suite
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nonconvex Gate Delay Modeling and Delay Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-synthesis leakage power minimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
High-performance gate sizing with a signoff timer
Proceedings of the International Conference on Computer-Aided Design
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Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discreteness of the problem, along with complex timing models, stringent constraints and ever increasing circuit sizes make the problem very difficult to tackle. Lagrangian Relaxation is an effective technique to handle complex constrained optimization problems and therefore has been used for gate sizing. In this paper, we propose an improved Lagrangian Relaxation formulation for leakage power minimization that accounts for maximum gate input slew and maximum gate output capacitance in addition to the circuit timing constraints. We also present a fast topological greedy heuristic to solve the Lagrangian Relaxation Subproblem and a complementary procedure to fix the few remaining slew and capacitace violations. The experimental results, generated by using the ISPD 2012 Discrete Gate Sizing Contest infrastructure, show that our technique is able to optimize a circuit with up to 959K gates within only 51 minutes. Comparing to the ISPD Contest top three teams, our technique obtained on average 18.9%, 16.7% and 43.8% less leakage power, while being 38, 31 and 39 times faster.