The ISPD-2012 discrete cell sizing contest and benchmark suite

Authors:
Muhammet Mustafa Ozdal;Chirayu Amin;Andrey Ayupov;Steven Burns;Gustavo Wilke;Cheng Zhuo
Affiliations:
Intel Corporation, Hillsboro, OR, USA;Intel Corporation, Hillsboro, OR, USA;Intel Corporation, Hillsboro, OR, USA;Intel Corporation, Hillsboro, OR, USA;Intel Corporation, Hillsboro, OR, USA;Intel Corporation, Hillsboro, OR, USA
Venue:
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Year:
2012

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Abstract

Circuit optimization is essential to minimize power consumption of designs while satisfying timing constraints. The CAD problem focused on in the ISPD-2012 Contest is simultaneous gate sizing and threshold voltage assignment. In this paper, we describe an overview of the contest objectives and the provided benchmark suite. Furthermore, some details are provided in terms of the standard cell library, timing models, and the evaluation metrics of the ISPD-2012 Contest.