Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
New parallel randomized algorithms for the traveling salesman problem
Computers and Operations Research - Special issue on the traveling salesman problem
A new hybrid optimization algorithm
Computers and Industrial Engineering - Special issue on computational intelligence for industrial engineering
Nested Partitions Method for Global Optimization
Operations Research
Proceedings of the 2003 international symposium on Low power electronics and design
Topics in parallel integer optimization
Topics in parallel integer optimization
An Optimization Framework for Product Design
Management Science
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose Parallel and Randomized cell Sizing (PaRS), a parallel and randomized algorithm and tool to solve the discrete gate sizing (cell sizing) problem on a grid. PaRS is formulated based on an optimization framework known as nested partitions which we adopt for the first time in the computer-aided design area. PaRS uses parallelism from a novel perspective to better identify the optimization direction. It achieves near-optimal solutions (under 1%) for minimizing the total power subject to meeting a delay constraint. The embarrassingly parallel nature of PaRS makes it highly scalable.We show small algorithm runtimes, in at most minutes for large benchmarks featuring over 47 000 cells. We make comparison with the optimal solution which we are able to generate using customized and parallel branch-and-bound implementation on a grid. Consequently, we are able to generate the optimal solution within hours. While the optimal algorithm uses up to 200 central processing units (CPUs) on our grid, PaRS achieves significant speedups and near-optimal solutions using only 20 CPUs. We also study the impact of varying number of CPUs in PaRS. Finally, we discuss a grid-based implementation using the "master-worker" framework.