Optimized power-delay curve generation for standard cell ICs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power delay tradeoff using the genetic algorithm
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and/or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay tradeoff curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce tradeoff curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 two-level examples are given