VLSI array processors
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Multirate systems and filter banks
Multirate systems and filter banks
Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low-power CMOS with supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimized power-delay curve generation for standard cell ICs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Getting High-Performance Silicon from System-Level Design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Monitoring Temperature in FPGA based SoCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An overview of a compiler for mapping MATLAB programs onto FPGAs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Overview of a compiler for synthesizing MATLAB programs onto FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
MDE-based approach for generalizing design space exploration
MODELS'10 Proceedings of the 13th international conference on Model driven engineering languages and systems: Part I
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We present a performance analysis framework that efficiently generates and analyzes hardware designs for computationally intensive signal processing applications. Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation. Cost functions provided by our framework allow the user to reduce the design space to a set of efficient hardware implementations that meet performance constraints. We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold. This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs. Our work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. We illustrate the efficiency and accuracy of our framework by generating finite impulse response filter structures used in several signal processing applications such as adaptive equalizers and quadrature mirror filters. The results show that hardware filter structures generated by our framework can achieve, on average, a 3 fold increase in power efficiency when compared to manually constructed designs.