Modeling and estimating leakage current in series-parallel CMOS networks

Authors:
Paulo F. Butzen;Andre I. Reis;Chris H. Kim;Renato P. Ribas
Affiliations:
Universidade Federal do Rio Grande do Sul, Porto Algre, Brazil;Nangate Inc, Herlev, Denmark;University of Minnesota, Minneapolis, MN;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

Citing 7
Cited 1

Library-less synthesis for static CMOS combinational logic circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Logical effort: designing fast CMOS circuits

Logical effort: designing fast CMOS circuits
Analysis and minimization techniques for total leakage considering gate oxide leakage

Proceedings of the 40th annual Design Automation Conference
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits

VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)

Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Active leakage power optimization for FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms

Proceedings of the 18th ACM Great Lakes symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results.