The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Digital oscillation-test method for delay and stuck-at fault testing of digital circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Defect Characteristics and Testing Strategies
IEEE Design & Test
Information-driven circuit synthesis with the pre-characterized gate libraries
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
DAG based library-free technology mapping
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An evolutionary approach for standard-cell library reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A methodology for transistor-efficient supergate design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ring oscillators for functional and delay test of latches and flip-flops
Proceedings of the 24th symposium on Integrated circuits and systems design
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This work presents an effective way for evaluating and validating ensembles of combinational CMOS gates and logic cell libraries. The major contributions include an innovative design methodology for such a kind of test vehicle, as well as a simple and flexible multi-operating mode circuit architecture. The resulting circuit is quite useful for cell library verification at different levels: in the EDA environment and on silicon prototyping. The proposed methodology can be applied for analysis taking into account the logic gate functionality, timing performance, power consumption and circuit operating impact of nanometer aging effects. Simulation results demonstrate the circuit operation, features and facilities described herein.