On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
On Multiple Path Propagating Tests for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference
Delay Testing with Clock Control: An Alternative to Enhanced Scan
Proceedings of the IEEE International Test Conference
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Design for Delay Testability in High-Speed Digital ICs
Journal of Electronic Testing: Theory and Applications
Bridging the Testing Speed Gap: Design for Delay Testability
ETW '00 Proceedings of the IEEE European Test Workshop
Mixed Signal DFT: A Concise Overview
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Testing digital low-pass filters using oscillation-based test
Microprocessors & Microsystems
Contributions to the evaluation of ensembles of combinational logic gates
Microelectronics Journal
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Testing delay faults is becoming critical in new deepsubmicron digital circuits. This paper introduces a newtechnique for delay and stuck-at fault testing in digitalintegrated circuits. The proposed technique consists ofsensitizing a path in the digital circuit under test andthen incorporating it in a ring oscillator to test for delayand stuck-at faults in the path. This procedure should beexercised for all or at least critical paths in the circuit.To establish oscillations, we should make sure that thereis an odd number of inverters in the loop. This techniquecan be used along with scan techniques or be implementedas a built-in self-test technique. Benchmark resultsconfirm the efficiency of the proposed technique.The technique has been implemented in practice for an 8-bit digital adder on a field programmable device.