CMOS combinational circuit sizing by stage-wise tapering

Authors:
S. Pullela;R. Panda;A. Dharchoudhury;G. Vijayan;D. Blaauw
Affiliations:
Monterey Design Systems, San Jose, CA;High Frequency Design Methods and Technology, Motorola Inc., Austin, TX;High Frequency Design Methods and Technology, Motorola Inc., Austin, TX;High Frequency Design Methods and Technology, Motorola Inc., Austin, TX;High Frequency Design Methods and Technology, Motorola Inc., Austin, TX
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

Citing 3
Cited 0

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Library-less synthesis for static CMOS combinational logic circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

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Abstract

We describe a fast (linear time) procedure to optimally size transistors in a chain of multi-input gates/stages. The fast sizing is used in a simultaneous sizing and restructuring optimization procedure, to accurately predict relative optimal performance of alternative circuit structures for a given total area. The idea extends the concept of optimally sizing a buffer chain, and uses tapering constants based on the position of a stage in a circuit, and the position of a transistor in a stack.