DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The fanout problem: from theory to practice
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
A heuristic algorithm for the fanout problem
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
Performance-oriented technology mapping
On the circuit implementation problem
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance optimization of digital circuits
Performance optimization of digital circuits
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
A simultaneous routing tree construction and fanout optimization algorithm
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Bounding Fan-out in Logical Networks
Journal of the ACM (JACM)
Concurrent logic restructuring and placement for timing closure
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An integrated algorithm for combined placement and libraryless technology mapping
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Performance optimization under rise and fall parameters
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the global fanout optimization problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing driven gate duplication: complexity issues and algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A Robust Solution to the Timing Convergence Problem in High-Performance Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Technology mapping is inherently a difficult problem. The current mapping algorithms cannot provide optimum solutions for minimum delay or area for industrial circuits in the presence of large gate libraries, complex design constraints, realistic & accurate delay models, and in the absence of interconnect load and delay information. Thus there is a need and scope for applying postmapping logic transformations, namely gate resizing, fanout optimization by buffering, gate replication, generalized DeMorgan transform, simple gate decomposition/collapsing, resynthesis & remapping, and pin permutation.