Canonical embedding of rectangular duals with applications to VLSI floorplanning
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Area minimization for hierarchical floorplans
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A unified approach to topology generation and area optimization of general floorplans
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Area minimization for floorplans
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cluster refinement for block placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
How good are slicing floorplans?
Proceedings of the 1997 international symposium on Physical design
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A methodology for fast FPGA floorplanning
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Slicing floorplans with range constraint
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Slicing floorplan with clustering constraints
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Fast placement approaches for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Using Tabu Search for Design Automation of VLSI Systems
Journal of Heuristics
A New Floorplanning Method for FPGA Architectural Research
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
How good are slicing floorplans?
Integration, the VLSI Journal
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In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during iterative improvement are proposed: (1) Partial Clustering, and (2) Module Restructuring. These strategies work for localizing nets connecting small modules in small regions, and conceal such small modules and their nets during the iterative improvement phase. This method is successful in reducing both area and wire length in addition to reducing the computational time required for optimization. Although our method only searches slicing floorplans, the results are superior to the results obtained even with non-slicing floorplans. We applied our method to the largest MCNC floorplan benchmark example, ami49, and industrial data. For the ami49 benchmark, we obtained results superior to any published results for both estimated area and routing results.