Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Hybrid floorplanning based on partial clustering and module restructuring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Rectilinear block placement using sequence-pair
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
ECBL: an extended corner block list with solution space including optimum placement
Proceedings of the 2001 international symposium on Physical design
VLSI block placement using less flexibility first principles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An optimum placement search algorithm based on extended corner block list
Journal of Computer Science and Technology
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Deterministic VLSI block placement algorithm using less flexibility first principle
Journal of Computer Science and Technology
Practical slicing and non-slicing block-packing without simulated annealing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Stairway compaction using corner block list and its applications with rectilinear blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Unified quadratic programming approach for mixed mode placement
Proceedings of the 2005 international symposium on Physical design
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We propose an iterative optimization approach for mixedmacro-cell and standard-cell placement, which minimizes the chipsize and interconnection wire length at the same time. We present abranch-and-bound algorithm which efficiently searches for the optimalsolution by evaluating all of the possible configurations on theselected cluster to minimize the gap distance between the ceilingand the floor. A virtual grid and permutation order are generateddynamically to eliminate redundant branches, which was the causeof much higher complexity in other approaches. Experimentalresults on the MCNC benchmark circuits show that the algorithmachieves very competitive results to manual design.