Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Cluster refinement for block placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Floorplan representations: Complexity and connections
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
A two-level search algorithm for 2D rectangular packing problem
Computers and Industrial Engineering
Rectangular multi-chart geometry images
SGP '06 Proceedings of the fourth Eurographics symposium on Geometry processing
On improved least flexibility first heuristics superior for packing and stock cutting problems
SAGA'05 Proceedings of the Third international conference on StochasticAlgorithms: foundations and applications
Lifetime improvement through runtime wear-based task mapping
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Physical-aware system-level design for tiled hierarchical chip multiprocessors
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Variable-Order Ant System for VLSI multiobjective floorplanning
Applied Soft Computing
Optimal rectangle packing: an absolute placement approach
Journal of Artificial Intelligence Research
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We propose a new floorplanner BloBB based on multi-level branch-and-bound. It is competitive with annealers in terms of runtime and solution quality. We empirically quantify the gap between optimal slicing and non-slicing floorplans by comparing optimal packings and best seen results. Optimal slicing and non-slicing packings for apte, xerox and hp are reported. We also discover that the soft versions of all MCNC benchmarks, except for apte, and all GSRC benchmarks can be packed with zero dead-space.Additionally, realistic floorplans often have blocks with similar dimensions, if design blocks, such as memories, are reused. We show that this greatly reduces the complexity of black-packing.