Variable-Order Ant System for VLSI multiobjective floorplanning

  • Authors:

  • Chyi-Shiang Hoo;Kanesan Jeevan;Velappa Ganapathy;Harikrishnan Ramiah

  • Affiliations:

  • Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia;Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia;Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia;Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia

  • Venue:
  • Applied Soft Computing
  • Year:
  • 2013

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Abstract

Floorplanning is crucial in VLSI chip design as it determines the time-to-market and the quality of the product. In this work, Variable-Order Ant System (VOAS) is developed and combined with a floorplan model namely Corner List (CL) to optimize the area and wirelength. CL is used to represent the floorplan layout. Although CL has proven to have the same search space and time complexity as Corner Sequence (CS), comparatively, CL has more corners to be selected. This compensates the sequence weakness, where modules can be placed freely onto the corners, which are not bounded by the floorplan contour. Two groups of ants, namely VOAS and reconnaissance ants, which will collaborate with each other to determine the local information, are introduced. Through this cooperation, VOAS ant can ascertain its local information greedily, based on the local search space information carried out by reconnaissance ants. Subsequently, VOAS ant proposes a new variable-order property to prioritize the global and local explorations. The variable-order property enables the ants in VOAS to weigh a better choice of modules for the floorplanning, based on the local and global information. The update rules of VOAS are modified in order to handle two-dimensional problem, such as VLSI floorplanning. VOAS shows improved results in terms of purely area optimization as well as composite function of area and wirelength, as compared to other state-of-the-art and recent floorplanning/placement algorithms based on Microelectronics Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) benchmarks.