Robust fixed-outline floorplanning through evolutionary search
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An orthogonal simulated annealing algorithm for large floorplanning problems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ant colony system application to macrocell overlap removal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Proceedings of the 2006 international workshop on System-level interconnect prediction
3-D floorplanning using labeled tree and dual sequences
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 international symposium on Physical design
An improved particle swarm optimizer for placement constraints
Journal of Artificial Evolution and Applications - Particle Swarms: The Second Decade
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A tree based novel representation for 3D-block packing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Moving block sequence and organizational evolutionary algorithm for general floorplanning
CIS'05 Proceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part I
Placement constraints and macrocell overlap removal using particle swarm optimization
ANTS'06 Proceedings of the 5th international conference on Ant Colony Optimization and Swarm Intelligence
A genetic algorithm for VLSI floorplanning using o-tree representation
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Variable-Order Ant System for VLSI multiobjective floorplanning
Applied Soft Computing
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We present an ordered tree (O tree) structure to represent nonslicing floorplans. The O tree uses only n(2+[lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n!22n-2/nl.5). This is very concise compared to a sequence pair representation that has O((n!)2) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n2(n/4e)n). The complexity of O tree is even smaller than a binary tree structure for slicing floorplan that has O(n!25n-3/n1.5) combinations. Given an O tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over previous central processing unit (CPU) intensive cluster refinement method