Corner sequence: a P-admissible floorplan representation with a worst case linear-time packing scheme

Authors:
Jai-Ming Lin;Yao-Wen Chang;Shih-Ping Lin
Affiliations:
Realtek Semiconductor Corporation, Hsinchu 300, Taiwan, R.O.C. and Department of Computer and Information Science, National Chiao Tung University, Hsinchu, 300, Taiwan, R.O.C.;Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.;Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2003

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Abstract

Floorplanning/placement allocates a set of modules into a chip so that no two modules overlap and some specified objective is optimized. To facilitate floorplanning/placement, we need to develop an efficient and effective representation to model the geometric relationship among modules. In this paper, we present a P-admissible representation, called corner sequence (CS), for nonslicing floorplans. CS consists of two tuples that denote the packing sequence of modules and the corners to which the modules are placed. CS is very effective and simple for implementation. Also, it supports incremental update during packing. In particular, it induces a generic worst case linear-time packing scheme that can also be applied to other representations. Experimental results show that CS achieves very promising results for a set of commonly used MCNC benchmark circuits.