Sensitivity analysis in polynomial geometric programming
Journal of Optimization Theory and Applications
Discrete Applied Mathematics - Special volume: viewpoints on optimization
An infeasible interior-point algorithm for solving primal and dual geometric programs
Mathematical Programming: Series A and B - Special issue: interior point methods in theory and practice
Data caches for superscalar processors
ICS '97 Proceedings of the 11th international conference on Supercomputing
A matrix synthesis approach to thermal placement
Proceedings of the 1997 international symposium on Physical design
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
Microprocessors & Microsystems
3D thermal-aware floorplanner using a MOEA approximation
Integration, the VLSI Journal
Variable-Order Ant System for VLSI multiobjective floorplanning
Applied Soft Computing
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With microprocessor power densities escalating rapidly when technology scales below nanometer regime, there is an exigent need for developing innovative cooling systems for electronic product design. The high temperature of chips greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling systems significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) for the optimization problem of temperature reduction and chip area floorplanning. We notice that the formulated model is a nonlinear convex problem; consequently, its solution can be solved GP method. Based upon an incremental floorplanning problem together with the GP model, the temperature-aware floorplanning scheme significantly reduces peak module temperature with minimal chip area impact. For Microelectronics Center of North Carolina (MCNC) ami33 under a testing environment temperature of 0 ^@?C, compared with the maximum temperature of the original module, the maximum temperature of the optimized one could be reduced from 90 ^@?C to 10 ^@?C, where the minimized chip area is about 700 mm^2. For the case of MCNC ami49, the maximum temperature reduction is 60 ^@?C (i.e., its reduction is from 65 ^@?C to 5 ^@?C) with a minimal chip area of 2500 mm^2. We have numerically found a floorplan which can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance simultaneously.