An optimal algorithm for area minimization of slicing floorplans
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A unified approach to topology generation and area optimization of general floorplans
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient approximation algorithms for floorplan area minimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hybrid floorplanning based on partial clustering and module restructuring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
On convex formulation of the floorplan area minimization problem
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Efficient list-approximation techniques for floorplan area minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Algorithms and theory of computation handbook
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Constraint-aware interior layout exploration for pre-cast concrete-based buildings
The Visual Computer: International Journal of Computer Graphics
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In this paper we study the area minimization problem in floorplanning (also known as the floorplan sizing problem). For a given floorplan, the problem is to select a layout alternative for each subcircuit on a chip so as to minimize the chip area. Two area minimization methods for general floorplans are proposed. Both methods can be viewed as generalizations of the classical algorithm for slicing floorplans of Otten (1982) and Stockmeyer (1983) in the sense that they reduce naturally to their algorithm for slicing floorplans. Compared with the branch-and-bound algorithm of Wimer et al (1989), which does not have a nontrivial performance bound, our methods are provably better than an exhaustive method for all the examples we examined