Optimal orientations of cells in slicing floorplan designs
Information and Control
An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient implementation of a scaling minimum-cost flow algorithm
Journal of Algorithms
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Revisiting floorplan representations
Proceedings of the 2001 international symposium on Physical design
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '82 Proceedings of the 19th Design Automation Conference
Convex Optimization
ACG-Adjacent Constraint Graph for General Floorplans
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Handling soft modules in general nonslicing floorplan using Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Twin binary sequences: a nonredundant representation for general nonslicing floorplan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area minimization for floorplans
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Linear constraint graph for floorplan optimization with soft blocks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multicore parallel min-cost flow algorithm for CAD applications
Proceedings of the 46th Annual Design Automation Conference
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning for low power IC design considering temperature variations
Microelectronics Journal
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
| Hi-index | 0.00 |
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lagrangian relaxation for the minimum area floorplanning problem. We show that the problem is not convex and its optimal solution cannot be obtained by solving its Lagrangian dual problem. We then propose a modified convex formulation and solve it using min-cost flow technique and trust region method. Experimental results under module aspect ratio bound [0.5, 2.0] show that the running time of our floorplanner scales well with the problem size in MCNC benchmark. Compared with the floorplanner in [27], our flooplanner is 9.5X faster for the largest case "ami49". It also generates a floorplan with smaller deadspace for almost all test cases. In addition, since the generated floorplan has an aspect ratio closer to 1, it is more friendly to packaging. Our floorplanner is also amicable to including interconnect cost and other physical design metrics.