Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 7th conference on Formal power series and algebraic combinatorics
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '82 Proceedings of the 19th Design Automation Conference
Module packing based on the BSG-structure and IC layout applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Twin binary sequences: a non-redundant representation for general non-slicing floorplan
Proceedings of the 2002 international symposium on Physical design
On the number of rectangular partitions
SODA '04 Proceedings of the fifteenth annual ACM-SIAM symposium on Discrete algorithms
On handling arbitrary rectilinear shape constraint
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
Handling routability in floorplan design with twin binary trees
Integration, the VLSI Journal
Investigating modern layout representations for improved 3d design automation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Floorplan representations are a fundamental issue in designing floorplan algorithms. In this paper, we first derive the exact number of configurations of mosaic floorplans and slicing floorplans. We then present two non-redundant representations: a twin binary tree structure for mosaic floorplans and a slicing ordered tree for slicing floorplans. Finally, the relations between the state-of-the-art floorplan representations are discussed and their efficiency is explored.