Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
VLSI/PCB placement with obstacles based on sequence-pair
Proceedings of the 1997 international symposium on Physical design
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with range constraint
ISPD '99 Proceedings of the 1999 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Revisiting floorplan representations
Proceedings of the 2001 international symposium on Physical design
VLSI floorplanning with boundary constraints based on corner block list
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Module placement with boundary constraints using the sequence-pair representation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list
Proceedings of the 38th annual Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with boundary constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Twin binary sequences: a nonredundant representation for general nonslicing floorplan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
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In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the most updated work on this problem by Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66-73], our algorithm can handle buses going through many blocks and the dead space of the floorplan obtained is also reduced. For example, if the buses have to go through more than 10 blocks, the approach in Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66-73] is not able to generate any solution while our algorithm can still give solutions of good quality.