Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
VLSI/PCB placement with obstacles based on sequence-pair
Proceedings of the 1997 international symposium on Physical design
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Rectilinear block placement using sequence-pair
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Topology constrained rectilinear block packing for layout reuse
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Arbitrary rectilinear block packing based on sequence pair
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with range constraint
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Arbitrary convex and concave rectilinear block packing using sequence-pair
ISPD '99 Proceedings of the 1999 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Placement constraints in floorplan design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
Performance-driven analog placement considering boundary constraint
Proceedings of the 47th Design Automation Conference
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In VLSI module placement, it is very practical to consider placing some modules along the pre-specified boundaries of the chip so that the modules are easier to be connected to certain I/O pads. In this paper, we study the module placement problem where some modules have the boundary constraints, and present a simulated annealing based algorithm that represents each placement topology by a sequence-pair. The major contribution of our algorithm is that a feasible placement is always obtainable. Our algorithm has been implemented, and its effectiveness is supported by the encouraging experimental results.