A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints

Authors:
Satoshi Tayu
Affiliations:
Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa, Japan
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

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Abstract

The module placement is one of the most important problem in the VLSI design. A practical VLSI placement problem often includes some constraints. In this paper, we propose a penalty function approach for the efficient simulated annealing search on the solution space of constrained problems. We apply the penalty function approach to the placement problem with boundary constraints. Experimental results show that our proposed method can accomplish more effective simulated annealing search than the conventional method proposed in [3] for two modules sets, an MCNC benchmark ami49 and a randomly generated module set.