Placement constraints in floorplan design

Authors:
Evangeline F. Y. Young;Chris C. N. Chu;M. L. Ho
Affiliations:
Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong;Department of Electrical and Computer Engineering, Iowa State University, Ames, IA;Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like datapath alignment and I/O connection. There are several previous works focusing on some particular kinds of placement constraints. In this paper, we will present a unified method to handle all of them simultaneously, including preplace constraint, range constraint, boundary constraint, alignment, abutment, and clustering, etc., in general, nonslicing floorplans. We have used incremental updates and an interesting idea of reduced graph to improve the runtime of the method. We tested our method using some benchmark data with about 1/8 of the modules having placement constraints and the results are very promising. Good packings with all the constraints satisfied can be obtained efficiently.