Simulated annealing for VLSI design
Simulated annealing for VLSI design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI/PCB placement with obstacles based on sequence pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Slicing floorplans with boundary constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Consistent floorplanning with super hierarchical constraints
Proceedings of the 2001 international symposium on Physical design
Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list
Proceedings of the 38th annual Design Automation Conference
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
An optimum placement search algorithm based on extended corner block list
Journal of Computer Science and Technology
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Stairway compaction using corner block list and its applications with rectilinear blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Abstraction and optimization of consistent floorplanning with pillar block constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Placement constraints in floorplan design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Non-slicing floorplans with boundary constraints using generalized polish expression
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
Performance-driven analog placement considering boundary constraint
Proceedings of the 47th Design Automation Conference
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In floorplanning of typical VLSI design, some modules are required to satisfy some placement constraints in the final packing. Boudary Constraint is one kind of those placement constraints to pack some modules along one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. We implement the boundary constraint algorithm for general floorplan by extending the Corner Block List (CBL) - a new efficient topology representation for non-slicing floorplan. Our contribution is to find the necessary and sufficient characterization of the modules along the boundary represented by Corner Block List. So that we can check the boundary constraints by scanning the intermediate solutions in the linear time during the simulated annealing process and fix the corner block list in case the constraints are violated. The experiment results are demonstrated by several examples of MCNC benchmarks and the performance is remarkable.