VLSI floorplanning with boundary constraints based on corner block list
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Placement constraints in floorplan design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Non-slicing floorplans with boundary constraints using generalized polish expression
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
Efficient package pin-out planning with system interconnects optimization for package-board codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A theoretical upper bound for IP-based floorplanning
COCOON'05 Proceedings of the 11th annual international conference on Computing and Combinatorics
Performance-driven analog placement considering monotonic current paths
Proceedings of the International Conference on Computer-Aided Design
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In floorplanning of very large scale integration design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom, or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplan algorithm to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solutions in the simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good