An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI floorplanning with boundary constraints based on corner block list
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Module packing based on the BSG-structure and IC layout applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Consistent floorplanning with hierarchical superconstraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Practicality on placement given by optimality of packing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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We aim at developing floorplan method, a key in topdown design of sytem LSIs, and provide floorplan abstraction available in high level design. We introduce pillar blocks to represent a frame of a chip layout and propose how to evaluate the chip before the floorplanning with physical dimension. The frame by the pillar blocks is employed as constraints in optimizing block placement. The experiments to MCNC benchmarks showed that the abstraction is faithful to the physically optimized block placement with respect to the chip area and the wire-length.