The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications

  • Authors:
  • Shigetoshi Nakatake;Keishi Sakanushi;Yoji Kajitani;Masahiro Kawakita

  • Affiliations:
  • Department of Electrical and Electronic Engineering, Tokyo Institute of Technology;Department of Electrical and Electronic Engineering, Tokyo Institute of Technology;Department of Electrical and Electronic Engineering, Tokyo Institute of Technology;Semiconductor Systems Engineering Center, Toshiba Corporation

  • Venue:
  • Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 1998

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Abstract