Simulated annealing for VLSI design
Simulated annealing for VLSI design
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Robust fixed-outline floorplanning through evolutionary search
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Placement with Alignment and Performance Constraints Using the B*-Tree Representation
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Module placement for fault-tolerant microfluidics-based biochips
Proceedings of the 41st annual Design Automation Conference
A stable fixed-outline floorplanning method
Proceedings of the 2007 international symposium on Physical design
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast wire length estimation by net bundling for block placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A simultaneous bus orientation and bused pin flipping algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
TCG-based multi-bend bus driven floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
Solving modern mixed-size placement instances
Integration, the VLSI Journal
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Timing variation-aware high-level synthesis considering accurate yield computation
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Algorithms and theory of computation handbook
Floorplanning considering IR drop in multiple supply voltages island designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast substrate noise aware floorplanning for mixed signal SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
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Unlike classical floorplanning that usually handles only block packing to minimize silicon area, modern VLSI floorplanning typically needs to pack blocks within a fixed die (outline) and additionally considers the packing with block positions and interconnect constraints. Floorplanning with bus planning is one of the most challenging modern floorplanning problems because it needs to consider the constraints with interconnect and block positions simultaneously. We study in this paper two types of modern floorplanning problems: (1) fixed-outline floorplanning and (2) bus-driven floorplanning. Our floorplanner uses the B*-tree floorplan representation and is based on a fast three-stage simulated annealing scheme, called Fast-SA. For fixed-outline floorplanning, we present an adaptive Fast-SA that can dynamically change the weights in the cost function to optimize wirelength under the outline constraint. Experimental results show that our floorplanner can achieve almost 100% success rates efficiently for fixed-outline floorplanning with various aspect ratios, compared to 10%--90% success rates obtained by the most recent works. For the bus-driven floorplanning, we explore the feasibility conditions of the B*-tree with the bus constraints and develop a bus-driven floorplanning algorithm based on the conditions and Fast-SA. Experimental results show that our floorplanner on the average reduces 20% (55%) dead space for the floorplanning with hard (soft) macro blocks, compared with the most recent work. In particular, our floorplanner is more efficient than the previous works.